Modern digital systems typically include one or more memory devices that are accessed through a memory controller. In a common application, the memory device(s) and memory controller reside on a printed circuit hoard (PCB), and the memory device(s) are coupled to the memory controller via one or more PCB signal lines.
In some applications, a memory system may include more than one (e.g., two) memory devices that are coupled to a memory controller via the PCB signal lines, with a first memory device on the same side of the PCB as the memory controller, and a second memory device on an opposite side of the PCB. The second memory device “mirrors” the first memory device and shares the PCB signal lines with the first memory device. The PCB signal lines may include signal lines for conveying data signals, signal lines for conveying strobe signals, and signal lines for conveying command/address (CA) signals between the controller and the memory devices.
The memory system is said to be an “N-bit wide” system when data is written to the memory devices and/or read from the memory devices “N-bits” at a time. Thus, the memory devices in such a system may be denoted as “by N” or “xN” memory devices. For example, the system may be a “byte-wide” system (N=8) in which data is transferred in 8-bit parallel fashion, and the memory devices are “x8” devices. During a write operation, a memory address is provided to indicate the desired destination of the data to be written (i.e. desired device and desired intra-device location). Once the desired destination is identified, N-bits of data are transmitted from the controller to the desired destination in the form of N parallel write-data signals. The N write-data signals are conveyed from the controller to the desired destination by respective ones of N data signal lines. In addition, a write strobe signal corresponding to the N bits is provided to the addressed memory device by way of a strobe signal line. The write strobe signal provides timing information to insure that the N data signals are correctly sampled at the destination.
During a read operation, a memory address is provided to indicate the memory location to be read. Once the location is identified (desired device and desired intra-device location) the N bits of data are transmitted from the memory location to the controller in the form of N parallel read-data signals. The N read-data signals are conveyed from the memory location to the controller by respective ones of the N data signal lines. In addition, a read strobe signal is provided to the controller by way of the strobe signal line. The read strobe signal provides timing information to insure that the N data signals are correctly sampled at the controller.
The timing of the strobe signal is critical for both write and read operations. In a write operation, the arrival of the write strobe signal at the addressed device may need to be synchronized with the arrival of the write-data signals such that the write-data signals are correctly sampled. In a read operation, the arrival of the read strobe signal at the controller may need to be synchronized with the arrival of the read-data signals such that the read-data signals are correctly sampled.